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RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 1 power management unit total power solution for ssd general description the RT5045A is a total power management solution for ssd (solid state drive) and applicable the dedicated powered by 3.3v or 5v input. RT5045A provides six step - down converters, one ldo and is designed to be flexible pmic for supporting different output load applications with regulated power sequence. RT5045A provides configurable outputs for core power of ssd cont roller, nand flash memory, i/o power and dram power. it supports dynamic voltag e scaling by a dedicated i 2 c interface and also apply low power mode to minimize the standby power consumption. applications ? solid state devices ordering information note : richtek products are : ? rohs compliant and compatible with the current requirements of ipc/jedec j - std - 020. ? sui table for use in snpb or pb - free soldering processes . features ? supply input voltage ra nge : 2. 9 v to 5.5v ? six high effici ency, low voltage buck co nverters ? up to 85% effi ciency at 10ma, and at half ra ted output curren t ? ch1 : 2.3v to 3 v in 25mv step, ou tput 4a max. ? ch2 : 0.9v to 1.6v in 25mv step, ou tput 1a max. ? ch3 : 1.5v to 2.1v in 25mv step, ou tput 1a max. ? ch4 : 0.7v to 1.3v in 25mv step, o utput 2a max. ? ch5 : 0.7v to 1.3v in 25mv step, outp ut 1a max. ? ch6 : 0.7v to 1.3v in 25mv step, o utput 3.5a max. ? ch2/3 2 mhz ch4/5/6 2.5mhz default switching frequ ency and prog rammable 1 to 3mhz ? 2 mhz default switching freq uency and program mable 0. 8 to 2. 3 mhz (ch1) ? v sel0 & vsel1 for programmable default output vol tage ? one low quiescent current ldo with ou tput 200ma max. ? low power m ode (lpm) for ultra lo w quies cent curr ent ? high - speed i 2 c interf aces for programming outp uts ? por threshold select ion and open - dr ain por indic ator ? power sequence control during sta rtup ? ovp, uvp, uvlo ? thermal shutdown prote ction simplified application circuit p a c k a g e t y p e w s c : w l - c s p - 5 2 b 3 . 1 9 x 3 . 5 9 ( b s c ) r t 5 0 4 5 a l d o c h 1 s s d p v i n 1 p v i n 2 p v i n 3 p v i n 4 p v i n 5 p v i n 6 a v d d s c l s d a v s e l 0 v s e l 1 p o r s e l p o r i 2 c v r v o l t d e f a u l t s e t t i n g p o r v t h s e l e c t i o n p o r i n f o r m a t i o n p v i n a v i n r t 5 0 4 5 a s w 1 f b 1 c h 2 s w 2 f b 2 c h 3 s w 3 f b 3 c h 4 s w 4 f b 4 c h 5 s w 5 f b 5 c h 6 s w 6 f b 6
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 2 pin configurations (top view) wl - csp - 52b 3.19x3.59 (bsc) mark ing information v s e l 0 p o r s e l p g n d l d o f b 1 p g n d 1 l x 1 p v i n 1 s c l s d a a g n d a v d d a g n d v s e l 1 p g n d 6 l x 6 p o r p v i n 6 p g n d f b 2 p g n d 2 p g n d p g n d p g n d 6 l x 6 f b 6 p v i n 6 f b 5 l x 5 p g n d 5 p v i n 2 f b 3 p v i n 3 l x 3 p g n d 3 / 4 l x 4 p v i n 4 f b 4 l x 2 p g n d p v i n 3 l x 3 p g n d 3 / 4 l x 4 p v i n 4 p v i n 5 p g n d p g n d 1 l x 1 p v i n 1 p g n d p g n d j 8 h 8 g 8 e 8 d 8 c 8 b 8 a 8 j 7 h 7 g 7 f 7 e 7 d 7 c 7 b 7 a 7 j 6 h 6 b 6 a 6 j 5 h 5 b 5 a 5 j 4 h 4 b 4 a 4 j 3 h 3 b 3 a 3 j 2 h 2 g 2 f 2 e 2 d 2 c 2 b 2 a 2 j 1 h 1 g 1 f 1 e 1 d 1 c 1 b 1 a 1 f 8 r t 5 0 4 5 a w s c : p r o d u c t n u m b e r y m d n n : d a t e c o d e r t 5 0 4 5 a w s c y m d n n
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 3 functional pin description pin no. pin name pin function a1 ldo ldo output. a2 scl i 2 c interface clock signal . a3 sda i 2 c interface data signal. a4, a6 agnd analog ground. a5 avdd analog power input for control logic and ldo input. a7 por power on reset information. when avdd > v porth , por = high level. when avdd < v porth C 100mv, por = low level. a8 fb6 ch6 buck converter output voltage feedback input. b1 fb1 ch1 buck converter output voltage feedback input. b2, b3, e7, f2, f7, g2, g7, h2 pgnd power ground . b4 porsel por threshold voltage select. b5 vsel0 power rails default voltage select pin0. pull down resistance 1.5m ? typ. b6 vsel1 power rails default voltage select pin1. pull down resistance 1.5m ? typ. b7, b8 pgnd6 ch6 buck converter power ground. c1, c2 pgnd1 ch1 buck converter power ground. c7, c8 lx6 ch6 buck converter switched output. d1, d2 lx1 ch1 buck converter switched output. d7, d8 pvin6 ch6 buck converter input. e1, e2 pvin1 ch1 buck converter input. e8 fb5 ch5 buck converter output voltage feedback input. f1 fb2 ch2 buck converter output voltage feedback input. f8 pgnd5 ch5 buck converter power ground. g1 pgnd2 ch2 buck converter power ground. g8 lx5 ch5 buck converter switched output. h1 lx2 ch2 buck converter switched output. h3, j3 pvin3 ch3 buck converter input. h4, j4 lx3 ch3 buck converter switched output. h5, j5 pgnd3/4 ch3 and ch4 buck converter power ground. h6, j6 lx4 ch4 buck converter switched output. h7, j7 pvin4 ch4 buck converter input. h8 pvin5 ch5 buck converter input. j1 pvin2 ch2 buck converter input. j2 fb3 ch3 buck converter output voltage feedback input. j8 fb4 ch4 buck converter output voltage feedback input.
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 4 function block diagram l x 1 p g n d 1 f b 1 p v i n 1 c h 1 l x 4 p g n d 4 f b 4 p v i n 4 c h 4 l d o a v d d l d o p o r 0 . 7 v t o 1 . 3 v 2 a a v d d a g n d p o w e r c o n t r o l l x 5 p g n d 5 f b 5 p v i n 5 0 . 7 v t o 1 . 3 v 1 a c h 5 l x 6 p g n d 6 f b 6 p v i n 6 0 . 7 v t o 1 . 3 v 3 . 5 a c h 6 1 . 6 5 6 v t o 2 . 1 6 v 2 . 3 v t o 3 v 0 . 2 a 2 . 3 v t o 3 v 4 a l x 2 p g n d 2 f b 2 p v i n 2 c h 2 0 . 9 v t o 1 . 6 v 1 a l x 3 p g n d 3 f b 3 p v i n 3 c h 3 1 . 5 v t o 2 . 1 v 1 a i 2 c v o l t a g e s e l e c t p o r s e l e c t s c l s d a v s e l 0 v s e l 1 p o r s e l
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 5 operation the RT5045A provides six synchronous buck regulators and one ldo to satisfy the entire power system of ssd. this device can communicate with processors through i2c interface for programming the voltage, monitoring the status, or in/out the power saving mode. buck converter the RT5045A incorporates six high - efficiency synchronous switching buck converters that deliver various voltages. ch1 features peak current mode architecture of buck converter. for preventing the unstable when duty > 50% traditionally, it adds external ramp and compensation to reduce duty cycle perturbation and stabilize the current loop. ch1 can operate up to 100% duty to let the lowest input voltage still maintain the regulator work. and the output voltag e will be the lowest input voltage decreases dropout voltage on the resistance of current path. unlike ch1, the control scheme of other buck converters are constant - on - time current mode for low output vo ltage, quick transient response. the buck converters have a full set of protection. buck over - current protection the buck converters provides over current protection by detecting low - side mosfet valley inductor current for ch2~ch6 and by detection high - side mosfet peak current for ch1. if the sensed inductor current is over the current limit threshold, the ocp will be triggered. when ocp is tripped, the buck converter will keep the over current threshold level until the ove r current condition is removed. buck under voltage protection the output voltages are c ontinuously monitored for under voltage protection. if the output voltage falls below 60% of the reference voltage, under voltage protection is triggered and then the high - side and low - side mosfet will turn off. the uvp circuit will turn off all rails and latched. the way to cannel the latched behavior is to re - give avdd power of RT5045A. buck output over voltage protection the output voltages are continuously monitored for over voltage protection. if the output voltage exceeds 120% of the reference, over voltage protection is triggered and then the high - side and low - side mosfet will turn off. the power mos will keep turn off until the ove r voltage condition is removed. linear dropout regulator the RT5045A includes one performance linear dropout regulators . the ldo contains an independent current limit and under voltage protection circuit to prevent unexpected applications. when the path current is over the current limit, the current limit circuit fixes the gate voltage to limit the output current. and if t he output voltage is less than 60% of reference voltage, the uvp circuit will shut - down all rails and latched. the way to cannel the latched behavior is to re - give avdd power of RT5045A. over - temperature protection if the temperature of the buck converter is over 150c, the otp circuit acts and makes all power rails shutdown. they recover back with power - up sequence when the tempe rature of pmic is low to 125c. vsel0, vsel1 the RT5045A applies four set default output voltages for all power rails when the d evice starts a power up sequence. porsel porsel is a logic pin to select the threshold voltage of avdd to raise por signal. if avdd voltage is over the threshold voltage, the device starts a por rising function. when set porsel = 1, the threshold voltage of avdd is 3.8v, else the threshold voltage is 2 .8v. por por pin is a signal to inform the system that the power up sequence of the RT5045A is completed. if avdd voltage is larger than the por rising threshold voltage, the por will go high with a timing delay. if avdd voltage is less than por falling threshold voltage, the por falls right away.
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 6 absolute maximum ratings (note 1 ) ? supply input voltage, avdd, pvin1, pvin2, pvin3, pvin4, pvin5, pvin6 --------------------------- ?? 0.3v to 6v ? switch node voltage, lx1, lx2, lx3, lx4, lx5, lx6 -------------------------------- ------------------------- ?? 0.3v to 6v ? other pins -------------------------------- -------------------------------- -------------------------------- ---------------- ?? 0.3v to 6v ? power dissipation, p d @ t a = 25 ? c wl - csp - 52b 3.19x3.59 (bsc) -------------------------------- -------------------------------- --------------------- ? 3.84 w ? package thermal resistance (note 2 ) wl - csp - 52b 3.19x3.59 (bsc) , ? ja -------------------------------- -------------------------------- --------------- ? 26 ? c/w ? lead temperature (soldering, 10 sec.) -------------------------------- -------------------------------- ----------- ? 260 ? c ? junction temperature -------------------------------- -------------------------------- -------------------------------- - ? 150 ? c ? storage temperature range -------------------------------- -------------------------------- ------------------------ ? ? 65 ? c to 150 ? c esd susceptibility (note 3 ) hbm (human body model) -------------------------------- -------------------------------- -------------------------- ? 2 kv recommended operating conditions (note 4 ) ? supply input voltage, avdd, pvin1, pvin2, pvin3, pvin4, pvin5, pvin6 --------------------------- ? 2. 9 v to 5.5v ? other p ins, vsel0, vsel1, scl, sda, porsel, por -------------------------------- --------------------- ? 0 v to 5.5v ? ambient temperature range -------------------------------- -------------------------------- ------------------------ ? ? 40 ? c to 85 ? c ? junction temperature range -------------------------------- -------------------------------- ----------------------- ?? 40 ? c to 125 ? c electrical characteristics ( avdd = 3.3v, pvin = 3.3v , t a = 25 ? c, unless otherwise specified) parameter symbol test conditions min typ max unit pmic avdd supply voltage v avin 2.9 3.3 5.5 v avdd supply current i avin all voltage rails off -- 15 25 ? a avdd supply current in sleep mode ch5 = lpm, other voltage rails off -- 15 25 ? a vsel0, vsel1, porsel high v ih logic signal rising threshold 1.2 -- -- v vsel0, vsel1, porsel low v il logic signal falling threshold -- -- 0.4 v avdd uvlo hysteresis hysteresis -- 100 -- mv avdd uvlo threshold v avuv por_option = 0, porsel = 0, uvlo falling 2.673 2. 7 2.727 v por_option = 0, porsel = 1, uvlo falling 3.663 3.7 3.737 avdd uvlo hysteresis hysteresis -- 100 -- mv por threshold v porth por_option = 0, porsel = 0, por falling 2.673 2. 7 2.727 v por_option = 0, porsel = 1, por falling 3.663 3.7 3.737 por hysteresis hysteresis -- 100 -- mv por output low v porlo sink current = 5ma -- -- 0.4 v
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 7 parameter symbol test conditions min typ max unit por rising delay time avdd > v porth , detect the por rising edge. vsel = 0, vsel1 = 0 9 10 11 ms thermal shutdown threshold t sd -- 150 -- ? c thermal shutdown hysteresis -- 25 -- ? c ch1 (4a) avdd quiescent current i inq enable, no switching , not include i avin -- 2 5 35 ? a avdd lpm quiescent i inlp lpm enable , not include i avin -- 10 20 ? a output voltage scaling controlled by i 2 c 2.3 -- 3 v output voltage default v out vsel0 = 0, vsel1 = 0 ? 2% 2.5 +2% v dc output voltage programmable step v step -- 25 -- mv line regulation -- 0.5 -- % /v load regulation force pwm -- 0.5 -- % /a transient load regulation v in = 3.3v, v out = 2. 5 v , l = 0.47 ? h, c out = 22 ? f x 2, i out = 0.2 to 1.5a at sr = 0.13a/ ? s -- -- 84 mv h/s switch on resistance r ds(on)h v in = 5 v -- 35 -- m ? l/s switch on resistance r ds(on)l v in = 5 v -- 18 -- m ? current limit i oc peak current, imax[6:5] = 10 5 5.8 -- a switching frequency f sw freq[2:0] = 110 1.8 2 2.2 mhz minimum on - time t o n -- 150 200 ns ovp trip threshold v ovp ovp detected 115 120 125 % ovp propagation delay t ovpdly -- 1 -- ? s uvp trip threshold v uvp uvp detected 55 60 65 % uvp propagation delay (note 5) t uvpdly -- 2 -- ? s soft - start time t ss -- 0.5 0.8 ms discharge resistance -- 50 -- ? efficiency v in = 3.3v, v out = 2.5v , load = 10ma 85 -- -- % v in = 3.3v, v out = 2.5v , load = 1a 90 -- -- ch2 (1a) avdd quiescent current i inq enable, no switching , not include i avin -- 2 5 35 ? a avdd lpm quiescent i inlp lpm enable , not include i avin -- 10 20 ? a output voltage scaling controlled by i 2 c 0.9 -- 1.6 v output voltage default v out vsel0 = 0, vsel1 = 0 ? 2% 1.35 +2% v dc output voltage programmable step v step -- 25 -- mv line regulation -- 0.5 -- % /v load regulation force pwm -- 0.5 -- % /a
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 8 parameter symbol test conditions min typ max unit transient load regulation v in = 3.3v, v out = 1.5v -- -- 75 mv h/s switch on resistance r ds(on)h v in = 5 v -- 40 -- m ? l/s switch on resistance r ds(on)l v in = 5 v -- 20 -- m ? current limit i oc v a lley current, imax[6:5] = 10 , 2 2.5 -- a switching frequency f sw freq[2:0] = 1 01 1.8 2 2.2 mhz minimum off - time t off -- 120 160 ns ovp trip threshold v ovp ovp detected 120 125 130 % ovp propagation delay t ovpdly 1 -- ? s uvp trip threshold v uvp uvp detected 55 60 65 % uvp propagation delay (note 5) t uvpdly -- 2 -- ? s soft - start time t ss -- 0.5 0.8 ms discharge resistance -- 100 -- ? efficiency v in = 3.3v, v out = 1.5v, load = 10ma 85 -- -- % v in = 3.3v, v out = 1.5v, load = 500ma 85 -- -- ch3 (1a) avdd quiescent current i inq enable, no switching , not include i avin -- 25 35 ? a avdd lpm quiescent i inlp lpm enable , not include i avin -- 10 20 ? a output voltage scaling controlled by i 2 c 1.5 -- 2.1 v output voltage default v out vsel0 = 0, vsel1 = 0 ? 2% 1.8 +2% v dc output voltage programmable step v step -- 25 -- mv line regulation -- 0.5 -- % /v load regulation force pwm -- 0.5 -- % /a transient load regulation v in = 3.3v, v out = 1.8v -- -- 90 mv h/s switch on resistance r ds(on)h v in = 5 v -- 45 -- m ? l/s switch on resistance r ds(on)l v in = 5 v -- 25 -- m ? current limit i oc valley current, imax[6:5] = 10 2 2.5 -- a switching frequency f sw freq[2:0] = 1 01 1.8 2 2.2 mhz minimum off - time t off -- 120 160 ns ovp trip threshold v ovp ovp detected 120 125 130 % ovp propagation delay t ovpdly -- 1 -- ? s uvp trip threshold v uvp uvp detected 55 60 65 % uvp propagation delay (note 5) t uvpdly -- 2 -- ? s soft - start time t ss -- 0.5 0.8 ms discharge resistance -- 50 -- ? efficiency v in = 3.3v, v out = 1.8v, load = 10ma 85 -- -- % v in = 3.3v, v out = 1.8v, load = 500ma 85 -- --
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 9 parameter symbol test conditions min typ max unit ch4 (2a) avdd quiescent current i inq enable, no switching , not include i avin -- 25 35 ? a avdd lpm quiescent i inlp lpm enable , not include i avin -- 10 2 0 ? a output voltage scaling controlled by i 2 c 0.7 -- 1.3 v output voltage default v out vsel0 = 0, vsel1 = 0 ? 2% 1 +2% v dc output voltage programmable step v step -- 25 -- mv line regulation -- 0.5 -- % /v load regulation force pwm -- 0.5 -- % /a transient load regulation v in = 3.3v, v out = 1v -- -- 50 mv h/s switch on resistance r ds(on)h v in = 5 v -- 45 -- m ? l/s switch on resistance r ds(on)l v in = 5 v -- 25 -- m ? current limit i oc valley current, imax[6:5] = 10 2.5 3 -- a switching frequency f sw freq[2:0] = 110 2.2 2.5 2.75 mhz minimum off - time t off -- 120 160 ns ovp trip threshold v ovp ovp detected 120 125 130 % ovp propagation delay t ovpdly -- 1 -- ? s uvp trip threshold v uvp uvp detected 55 60 65 % uvp propagation delay (note 5) t uvpdly -- 2 -- ? s soft - start time t ss -- 0.5 0.8 ms discharge resistance t dis -- 15 0 -- ? efficiency v in = 3.3v, v out = 1v, load = 10ma 85 -- -- % v in = 3.3v, v out = 1v, load = 1a 85 -- -- ch5 (1a) avdd quiescent current i inq enable, no switching , not include i avin -- 25 35 ? a avdd lpm quiescent i inlp lpm enable , not include i avin -- 10 20 ? a output voltage scaling controlled by i 2 c 0.7 -- 1.3 v output voltage default v out vsel0 = 0, vsel1 = 0 ? 2% 1 +2% v dc output voltage programmable step v step -- 25 -- mv line regulation -- 0.5 -- % /v load regulation force pwm -- 0.5 -- % /a transient load regulation v in = 3.3v, v out = 1v -- -- 50 mv h/s switch on resistance r ds(on)h v in = 5 v -- 50 -- m ? l/s switch on resistance r ds(on)l v in = 5 v -- 30 -- m ? current limit i oc valley current, imax[6:5] = 10 2 2.5 -- a switching frequency f sw freq[2:0] = 110 2.2 2.5 2.75 mhz minimum off - time t off -- 120 160 ns
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 10 parameter symbol test conditions min typ max unit ovp trip threshold v ovp ovp detected 120 125 130 % ovp propagation delay t ovpdly -- 1 -- ? s uvp trip threshold v uvp uvp detected 55 60 65 % uvp propagation delay (note 5) t uvpdly -- 2 -- ? s soft - start time t ss -- 0.5 0.8 ms discharge resistance -- 15 0 -- ? efficiency v in = 3.3v, v out = 1v, load = 1ma, lpm 85 -- -- % v in = 3.3v, v out = 1v, load = 500ma 85 -- -- ch6 (3.5a) avdd quiescent current i inq enable, no switching , not include i avin -- 25 35 ? a avdd lpm quiescent i inlp lpm enable , not include i avin -- 10 20 ? a output voltage scaling controlled by i 2 c 0.7 -- 1.3 v output voltage default v out vsel0 = 0, vsel1 = 0 ? 2% 1 +2% v dc output voltage programmable step v step -- 25 -- mv line regulation -- 0.5 -- % /v load regulation force pwm -- 0.5 -- % /a transient load regulation v in = 3.3v, v out = 1v -- -- 50 mv h/s switch on resistance r ds(on)h v in = 5 v -- 40 -- m ? l/s switch on resistance r ds(on)l v in = 5 v -- 20 -- m ? current limit i oc valley current, imax[6:5] = 10 4.5 5 -- a switching frequency f sw freq[2:0] = 110 2.2 2.5 2.75 mhz minimum off - time t off -- 120 160 ns ovp trip threshold v ovp ovp detected 120 125 130 % ovp propagation delay t ovpdly -- 1 -- ? s uvp trip threshold v uvp uvp detected 55 60 65 % uvp propagation delay (note 5) t uvpdly -- 2 -- ? s soft - start time t ss -- 0.5 0.8 ms discharge resistance -- 15 0 -- ? efficiency v in = 3.3v, v out = 1v, load = 10ma 85 -- -- % v in = 3.3v, v out = 1v, load = 1a 85 -- -- ldo (0.2a) avdd quiescent current i inq enable , not include i avin -- 28 38 ? a avdd lpm quiescent i inlp lpm enable, not include i avin -- 15 25 ? a output voltage scaling vsel0 = 0, vsel1 = 0 vsel0 = 0, vsel1 = 1 2.3 -- 3 v vsel0 = 1, vsel1 = 0 vsel0 = 1, vsel1 = 1 1.656 -- 2.16
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 11 parameter symbol test conditions min typ max unit output voltage default v out vsel0 = 0, vsel1 = 0 ? 2% 2.5 +2% v dc output voltage programmable step v step -- 25 -- mv line regulation -- 0.5 -- % /v load regulation -- 0.5 -- % /a transient load regulation v in = 3.3v, v out = 2.5v, load = 20ma to 180ma during 5 ? s -- -- 125 mv dropout voltage v drop v in = 3.3v, v out = 2.5v load = 200ma -- 100 200 mv current limit i oc -- 0.4 -- a uvp trip threshold v uvp uvp detected 55 60 65 % uvp propagation delay (note 5) t uvpdly -- 2 -- ? s soft - start time t ss -- 0.3 0.6 ms discharge resistance t dis -- 1 00 -- ? power supply rejection rate psrr load = 100ma, f = 100hz -- ? 50 -- db load = 100ma, f = 10 0k hz -- ? 2 8 -- i 2 c for fast mode parameter symbol test conditions min typ max unit sda, scl input voltage high - level 1. 2 -- -- v low - level -- -- 0.4 fast mode scl clock rate f scl -- -- 400 khz hold time ( r epeated) start condition. after this period, the first clock pulse is generated t hd;sta 0.6 -- -- ? s low period of the scl clock t low 1.3 -- -- ? s high period of the scl clock t high 0.6 -- -- ? s set - up time for a repeated start condition t su;sta 0.6 -- -- ? s data hold time t hd;dat 0 -- 0.9 ? s data set - up time t su;dat 100 -- -- ns set - up time for stop condition t su;sto 0.6 -- -- ? s bus free time between a stop and start condition t buf 1.3 -- -- ? s ris ing time of both sda and scl signals t r 20 -- 300 ns fall ing time of both sda and scl signals t f 20 -- 300 ns sda and scl output low sink current i ol sda or scl v oltage = 0.4v 2 -- -- ma
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 12 i 2 c high speed mode parameter symbol test conditions min typ max unit sda, scl input voltage high - level 1. 2 -- -- v low - level -- -- 0.4 high speed mode scl clock rate f scl -- -- 3.4 m hz hold time ( r epeated) start condition. after this period, the first clock pulse is generated t hd;sta 160 -- -- n s low period of the scl clock t low 160 -- -- n s high period of the scl clock t high 60 -- -- n s set - up time for a repeated start condition t su;sta 60 -- -- n s data hold time t hd;dat 0 -- 70 n s data set - up time t su;dat 10 -- -- ns set - up time for stop condition t su;sto 160 -- -- n s ris ing time of both sda and scl signals t r 10 -- 80 ns fall ing time of both sda and scl signals t f 10 -- 80 ns sda and scl output low sink current i ol sda or scl v oltage = 0.4v 2 -- -- ma note 1. stresses beyond those listed absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ? ja is measured at t a = 25 ? c on a high effective thermal conductivity four - l ayer test board per jedec 51 - 7. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function ou tside its operating conditions. note 5. design guaranteed.
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 13 typical application circuit r t 5 0 4 5 a h 7 , j 7 p v i n 4 p v i n e 1 , e 2 p v i n 1 p v i n d 1 , d 2 l x 1 c h 1 , 4 a b 1 f b 1 0 . 4 7 h v s e l 1 b 6 v s e l 0 b 5 s d a a 3 s c l a 2 p g n d 1 0 f l x 4 c h 4 , 2 a j 8 f b 4 0 . 4 7 h h 6 , j 6 2 2 f j 5 p g n d 4 c 1 , c 2 p g n d 1 1 0 f x 2 2 2 f x 2 h 8 p v i n 5 p v i n j 1 p v i n 2 p v i n h 1 l x 2 c h 2 , 1 a f 1 f b 2 0 . 4 7 h 1 0 f l x 5 c h 5 , 1 a e 8 f b 5 0 . 4 7 h g 8 2 2 f f 8 p g n d 5 g 1 p g n d 2 1 0 f 2 2 f d 7 , d 8 p v i n 6 p v i n h 3 , j 3 p v i n 3 p v i n h 4 , j 4 l x 3 c h 3 , 1 a j 2 f b 3 0 . 4 7 h 1 0 f x 2 l x 6 c h 6 , 3 . 5 a a 8 f b 6 0 . 4 7 h c 7 , c 8 2 2 f x 2 b 7 , b 8 p g n d 6 h 5 p g n d 3 1 0 f 2 2 f p o r a 7 p o r s e l b 4 2 . 2 k 2 . 2 k 1 0 0 k a v i n a 5 a v d d a v i n 2 . 2 f a 4 , a 6 a g n d a 1 l d o l d o , 0 . 2 a 4 . 7 f b 2 , b 3 , e 7 , f 2 , f 7 , g 2 , g 7 , h 2
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 14 functional register table table 1 . RT5045A register summary name type register reset address offset power_good ro 0x00 0x00 ch1_cfg_reg rw 0x5 6 0x01 ch1_sel_reg rw 0x00 0x02 ch2_cfg_reg rw 0x5 5 0x03 ch2_sel_reg rw 0x00 0x04 ch3_cfg_reg rw 0x5 5 0x05 ch3_sel_reg rw 0x00 0x06 ch4_cfg_reg rw 0x56 0x07 ch4_sel_reg rw 0x00 0x08 ch5_cfg_reg rw 0x56 0x09 ch5_sel_reg rw 0x00 0x0a ch6_cfg_reg rw 0x56 0x0b ch6_sel_reg rw 0x00 0x0c ldo_sel_reg rw 0x00 0x0d dcdcctrl0_reg rw 0x00 0x11 sleep_reg rw 0x00 0x12 dcdcctrl1_reg rw 0x00 0x13 discharge_reg rw 0xfe 0x14 por_option_reg rw 0x00 0x17 dcdctrl2_reg rw 0x00 0x18 wk_time1 rw 0x00 0x19 wk_time2 rw 0x00 0x1a wk_time3 rw 0x00 0x1b wk_time4 rw 0x00 0x1c product_id_reg ro 0x01 0x20 manufacturer_id ro 0x01 0x21 revision_number ro 0x00 0x22
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 15 table 2 . power_good_reg address : 0x00 description : power good information register. when voltage rails achieve 90% of vid target, the relative bit will set to 1. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch1_pg ch 2 _pg ch 3 _pg ch 4 _pg ch 5 _pg ch 6 _pg ldo_pg por reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r bits name description 7 ch1_pg status bit. indicates power good on ch1 6 ch2_pg status bit. indicates power good on ch2 5 ch3_pg status bit. indicates power good on ch3 4 ch4_pg status bit. indicates power good on ch4 3 ch5_pg status bit. indicates power good on ch5 2 ch6_pg status bit. indicates power good on ch6 1 ldo _pg status bit. indicates power good on ldo 0 por status bit. indicates por table 3 . ch1_cfg_reg address : 0x01 description : ch1 config register. set ch1 current limited, vid change slew rate, pwm frequency. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved ilmax tstep freq reset value 0 1 0 1 0 1 1 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 5 ilmax ilmax[ 6:5 ] = 00 : 3. 8 a ilmax[ 6:5 ] = 01 : 4 . 8 a ilmax[ 6:5 ] = 10 : 5. 8 a ( default) ilmax[ 6:5 ] = 11 : 6. 8 a 4 : 3 tstep tstep[ 4:3 ] = 00 : 20mv/ ? ? ? ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 16 table 4 . ch1_sel_reg address : 0x02 description : ch1 vid setting register. ch1 vid setting and power on/off status and control. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved sel reserved reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 2 sel supply voltage, sel[6:2] = 00000 to 00011 : 2.3v sel[ 6:2 ] = 100 : 2.325v sel[6:2] = 101 : 2.35v sel[6:2] = 110 : 2.375v sel[6:2] = 111 : 2.4v sel[6:2] = 1000 : 2.425v sel[6:2] = 1001 : 2.45v sel[6:2] = 1010 : 2.475v sel[6:2] = 1011 : 2.5v sel[6:2] = 1100 : 2.525v sel[6:2] = 1110 : 2.575v sel[6:2] = 1111 : 2.6v sel[6:2] = 10000 : 2.625v sel[6:2] = 10001 : 2.65v sel[6:2] = 10010 : 2.675v sel[6:2] = 10011 : 2.7v sel[6:2] = 10100 : 2.725v sel[6:2] = 10101 : 2.75v sel[6:2] = 10110 : 2.775v sel[6:2] = 10111 : 2.8v sel[6:2] = 11000 : 2.825v sel[6:2] = 11001 : 2.85v sel[6:2] = 11010 : 2.875v sel[6:2] = 11011 : 2.9v sel[6:2] = 11100 : 2.925v sel[6:2] = 11111 : 3v vout = sel[6:2] x 0.025v + 2.225v, from sel[6:2] = 3 to 1f ( hex ) (after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : vsel0 = 0, vsel1 = 0, vout = 2. 5 v vsel0 = 0, vsel1 = 1, vout = 2.5v vsel0 = 1, vsel1 = 0, vout = 2.5v vs el0 = 1, vsel1 = 1, vout = 2.5v ) 1 : 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 17 table 5 . ch2_cfg_reg address : 0x03 description : ch2 config register. set ch2 current limited, vid change slew rate, pwm frequency. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved ilmax tstep freq reset value 0 1 0 1 0 1 0 1 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 5 ilmax ilmax[ 6 : 5 ] = 00 : 1.5a ilmax[ 6 : 5 ] = 01 : 2a ilmax[ 6 : 5 ] = 10 : 2.5a ( default) ilmax[ 6 : 5 ] = 11 : 3a 4 : 3 tstep tstep[ 4:3 ] = 00 : 20mv/ ? ? ? ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 18 table 6 . ch2_sel_reg address : 0x04 description : ch2 vid setting register. ch2 vid setting and power on/off status and control. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved sel reserved reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 2 sel supply voltage, sel[6:2] = 00000 to 00011 : 0.9v sel[6:2] = 100 : 0.925v sel[6:2] = 101 : 0.95v sel[6:2] = 110 : 0.975v sel[6:2] = 111 : 1v sel[6:2] = 1000 : 1.025v sel[6:2] = 1001 : 1.05v sel[6:2] = 1010 : 1.075v sel[6:2] = 1011 : 1.1v sel[6:2] = 1100 : 1.125v sel[6:2] = 1110 : 1.175v sel[6:2] = 1111 : 1.2v sel[6:2] = 10000 : 1.225v sel[6:2] = 10001 : 1.25v sel[6:2] = 10010 : 1.275v sel[6:2] = 10011 : 1.3v sel[6:2] = 10100 : 1.325v sel[6:2] = 10101 : 1.35v sel[6:2] = 10110 : 1.375v sel[6:2] = 10111 : 1.4v sel[6:2] = 11000 : 1.425v sel[6:2] = 11001 : 1.45v sel[6:2] = 11010 : 1.475v sel[6:2] = 11011 : 1.5v sel[6:2] = 11100 : 1.525v sel[6:2] = 11111 : 1.6v vout = sel[6:2] x 0.025v + 0.825v, from sel[6:2] = 3 to 1f ( hex ) (after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : vsel0 = 0, vsel1 = 0, vout = 1. 35 v vsel0 = 0, vsel1 = 1, vout = 1.35v vsel0 = 1, vsel1 = 0, vout = 1.35v vs el0 = 1, vsel1 = 1, vout = 1. 2 v ) 1 : 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 19 table 7 . ch3_cfg_reg address : 0x05 description : ch3 config register. set ch3 current limited, vid change slew rate, pwm frequency. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved ilmax tstep freq reset value 0 1 0 1 0 1 0 1 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 5 ilmax ilmax[ 6:5 ] = 00 : 1.5a ilmax[ 6:5 ] = 01 : 2a ilmax[ 6:5 ] = 10 : 2.5a (default ) ilmax[ 6:5 ] = 11 : 3a 4 : 3 tstep tstep[ 4:3 ] = 00 : 20mv/ ? ? ? ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 20 table 8 . ch3_sel_reg address : 0x06 description : ch3 vid setting register. ch3 vid setting and power on/off status and control. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved sel reserved reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 2 sel supply voltage, sel[6:2] = 00000 to 00011 : 1.5v sel[6:2] = 100 : 1.525v sel[6:2] = 101 : 1.55v sel[6:2] = 110 : 1.575v sel[6:2] = 111 : 1.6v sel[6:2] = 1000 : 1.625v sel[6:2] = 1001 : 1.65v sel[6:2] = 1010 : 1.675v sel[6:2] = 1011 : 1.7v sel[6:2] = 1100 : 1.725v sel[6:2] = 1110 : 1.775v sel[6:2] = 1111 : 1.8v sel[6:2] = 10000 : 1.825v sel[6:2] = 10001 : 1.85v sel[6:2] = 10010 : 1.875v sel[6:2] = 10011 : 1.9v sel[6:2] = 10100 : 1.925v sel[6:2] = 10101 : 1.95v sel[6:2] = 10110 : 1.975v sel[6:2] = 10111 : 2v sel[6:2] = 11000 : 2.025v sel[6:2] = 11001 : 2.05v sel[6:2] = 11010 : 2.075v sel[6:2] = 1101 1 to 11111 : 2.1v vout = sel[6:2] x 0.025v + 1.425v, from sel[6:2] = 3 to 1b ( hex ) (after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : vsel0 = 0, vsel1 = 0, vout = 1.8v vsel0 = 0, vsel1 = 1, vout = 1.8v vsel0 = 1, vsel1 = 0, vout = 1.8v vsel0 = 1, vsel1 = 1, vout = 1.8v) 1 : 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 21 table 9 . ch4_cfg_reg address : 0x07 description : ch4 config register. set ch4 current limited, vid change slew rate, pwm frequency. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved ilmax tstep freq reset value 0 1 0 1 0 1 1 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 5 ilmax ilmax[ 6:5 ] = 00 : 2a ilmax[ 6:5 ] = 01 : 2.5a ilmax[ 6:5 ] = 10 : 3a ( default) ilmax[ 6:5 ] = 11 : 3.5a 4 : 3 tstep tstep[ 4:3 ] = 00 : 20mv/ ? ? ? ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 22 table 10 . ch4_sel_reg address : 0x08 description : ch4 vid setting register. ch4 vid setting and power on/off status and control. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved sel reserved reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 2 sel supply voltage, sel[6:2] = 00000 : 0.7v sel[6:2] = 1 : 0.725v sel[6:2] = 10 : 0.75v sel[6:2] = 11 : 0.775v sel[6:2] = 100 : 0.8v sel[6:2] = 101 : 0.825v sel[6:2] = 110 : 0.85v sel[6:2] = 111 : 0.875v sel[6:2] = 1000 : 0.9v sel[6:2] = 1001 : 0.925v sel[6:2] = 1010 : 0.95v sel[6:2] = 1011 : 0.975v sel[6:2] = 1100 : 1v sel[6:2] = 1110 : 1.05v sel[6:2] = 1111 : 1.075v sel[6:2] = 10000 : 1.1v sel[6:2] = 10001 : 1.125v sel[6:2] = 10010 : 1.15v sel[6:2] = 10011 : 1.175v sel[6:2] = 10100 : 1.2v sel[6:2] = 10101 : 1.225v sel[6:2] = 10110 : 1.25v sel[6:2] = 10111 : 1.275v sel[6:2] = 11000 to 11111 : 1.3v vout = sel[6:2] x 0.025v + 0.7v, from sel[6:2] = 0 to 18 ( hex ) (after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : vsel0 = 0, vsel1 = 0, vout = 1.0v vsel0 = 0, vsel1 = 1, vout = 1.0v vsel0 = 1, vsel1 = 0, vout = 1. 2 v vsel0 = 1, vsel1 = 1, vout = 1. 2 v) 1 : 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 23 table 11 . ch5_cfg_reg address : 0x09 description : ch5 config register. set ch5 current limited, vid change slew rate, pwm frequency. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved ilmax tstep freq reset value 0 1 0 1 0 1 1 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 5 ilmax ilmax[ 6:5 ] = 00 : 1.5a ilmax[ 6:5 ] = 01 : 2.0a ilmax[ 6:5 ] = 10 : 2.5a (default) ilmax[ 6:5 ] = 11 : 3a 4 : 3 tstep tstep[ 4:3 ] = 00 : 20mv/ ? ? ? ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 24 table 12 . ch5_sel_reg address : 0x0a description : ch5 vid setting register. ch5 vid setting and power on/off status and control. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved sel reserved reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 2 sel supply voltage, sel[6:2] = 00000 : 0.7v sel[6:2] = 1 : 0.725v sel[6:2] = 10 : 0.75v sel[6:2] = 11 : 0.775v sel[6:2] = 100 : 0.8v sel[6:2] = 101 : 0.825v sel[6:2] = 110 : 0.85v sel[6:2] = 111 : 0.875v sel[6:2] = 1000 : 0.9v sel[6:2] = 1001 : 0.925v sel[6:2] = 1010 : 0.95v sel[6:2] = 1011 : 0.975v sel[6:2] = 1100 : 1v sel[6:2] = 1110 : 1.05v sel[6:2] = 1111 : 1.075v sel[6:2] = 10000 : 1.1v sel[6:2] = 10001 : 1.125v sel[6:2] = 10010 : 1.15v sel[6:2] = 10011 : 1.1 75v sel[6:2] = 10100 : 1.2v sel[6:2] = 10101 : 1.225v sel[6:2] = 10110 : 1.25v sel[6:2] = 10111 : 1.275v sel[6:2] = 11000 to 11111 : 1.3v vout = sel[6:2] x 0.025v + 0.7v, from sel[6:2] = 0 to 18 ( hex ) (after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : v sel0 = 0, vsel1 = 0, vout = 1 .0 v vsel0 = 0, vsel1 = 1, vout = 1 .0 v vsel0 = 1, vsel1 = 0, vout = 0.9 v vsel0 = 1, vsel1 = 1, vout = 0.9 v) 1 : 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 25 table 13 . ch6_cfg_reg address : 0x0b description : ch6 config register. set ch6 current limited, vid change slew rate, pwm frequency. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved ilmax tstep freq reset value 0 1 0 1 0 1 1 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 5 ilmax ilmax[ 6:5 ] = 00 : 4a ilmax[ 6:5 ] = 01 : 4.5a ilmax[ 6:5 ] = 10 : 5a (default) ilmax[ 6:5 ] = 11 : 5.5a 4 : 3 tstep tstep[ 4:3 ] = 00 : 20mv/ ? ? ? ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 26 table 14 . ch6_sel_reg address : 0x0c description : ch6 vid setting register. ch5 vid setting and power on/off status and control. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved sel reserved reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 2 sel supply voltage, sel[6:2] = 00000 : 0.7v sel[6:2] = 1 : 0.725v sel[6:2] = 10 : 0.75v sel[6:2] = 11 : 0.775v sel[6:2] = 100 : 0.8v sel[6:2] = 101 : 0.825v sel[6:2] = 110 : 0.85v sel[6:2] = 111 : 0.875v sel[6:2] = 1000 : 0.9v sel[6:2] = 1001 : 0.925v sel[6:2] = 1010 : 0.95v sel[6:2] = 1011 : 0.975v sel[6:2] = 1100 : 1v sel[6:2] = 1110 : 1.05v sel[6:2] = 1111 : 1.075v sel[6:2] = 10000 : 1.1v sel[6:2] = 10001 : 1.125v sel[6:2] = 10010 : 1.15 v sel[6:2] = 10011 : 1.175v sel[6:2] = 10100 : 1.2v sel[6:2] = 10101 : 1.225v sel[6:2] = 10110 : 1.25v sel[6:2] = 10111 : 1.275v sel[6:2] = 11000 to 11111 : 1.3v vout = sel[6:2] x 0.025v + 0.7v, from sel[6:2] = 0 to 18 ( hex ) (after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : vsel0 = 0, vsel1 = 0, vout = 1 .0 v vsel0 = 0, vsel1 = 1, vout = 1 .0 v vsel0 = 1, vsel1 = 0, vout = 0.9 v vs el0 = 1, vsel1 = 1, vout = 0.9 v ) 1 : 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 27 table 15 . ldo_sel_reg address : 0x0d description : ldo vid setting register. ldo vid setting and power on/off status and control. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved sel reserved reset value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w bits name description 7 reserved reserved bit 6 : 2 sel supply voltage . after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : vsel0 = 0, vsel1 = 0, vout = 2. 5 v vsel0 = 0, vsel1 = 1, vout = 2. 5 v sel[6:2] = 00000 to 00011 : 2.3v sel[6:2] = 100 : 2.325v sel[6:2] = 101 : 2.35v sel[6:2] = 110 : 2.375v sel[6:2] = 111 : 2.4v sel[6:2] = 1000 : 2.425v sel[6:2] = 1001 : 2.45v sel[6:2] = 1010 : 2.475v sel[6:2] = 1011 : 2.5v sel[6:2] = 1100 : 2.525v sel[6:2] = 1110 : 2.575v sel[6:2] = 1111 : 2.6v sel[6:2] = 10000 : 2.625v sel[6:2] = 10001 : 2.65v sel[6:2] = 10010 : 2.675v sel[6:2] = 10011 : 2.7v sel[6:2] = 10100 : 2.725v sel[6:2] = 10101 : 2.75v sel[6:2] = 10110 : 2.775v sel[6:2] = 10111 : 2.8v sel[6:2] = 11000 : 2.8 25v sel[6:2] = 11001 : 2.85v sel[6:2] = 11010 : 2.875v sel[6:2] = 11011 : 2.9v sel[6:2] = 11100 : 2.925v sel[6:2] = 1110 1 : 2.9 5 v sel[6:2] = 111 10 : 2.9 7 5v sel[6:2] = 11111 : 3v vout = sel[6:2] x 0.025v + 2.225v, from sel[6:2] = 3 to 1f ( hex ) after each uvlo rising, the voltage is set to the value by vsel0/vsel1 setting : vsel0 = 1, vsel1 = 0, vout = 1.8 v vsel0 = 1, vsel1 = 1, vout = 1.8 v sel[6:2] = 00000 to 00011 : 1.656 v sel[6:2] = 100 : 1.674v sel[6:2] = 101 : 1.692v sel[6:2] = 110 : 1.71v sel[6:2] = 111 : 1.728v sel[6:2] = 1000 : 1.746v sel[6:2] = 1001 : 1.764v
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 28 6 : 2 sel sel[6:2] = 1010 : 1.782v sel[6:2] = 1011 : 1.8v sel[6:2] = 1100 : 1.818v sel[6:2] = 110 1 : 1.8 36 v sel[6:2] = 1110 : 1.854v sel[6:2] = 1111 : 1.872v sel[6:2] = 10000 : 1.89v sel[6:2] = 10001 : 1.908v sel[6:2] = 10010 : 1.926v sel[6:2] = 10011 : 1.944v sel[6:2] = 10100 : 1.962v sel[6:2] = 10101 : 1.98v sel[6:2] = 10110 : 1.998v sel[6:2] = 10111 : 2.016v sel[6:2] = 11000 : 2.034v sel[6:2] = 11001 : 2.052v sel[6:2] = 11010 : 2.07v sel[6:2] = 11011 : 2.088v sel[6:2] = 11100 : 2.106v sel[6:2] = 1110 1 : 2.1 24 v sel[6:2] = 111 10 : 2.1 42 v sel[6:2] = 11111 : 2.16v 1 : 0 reserved reserved bit table 16 . dcdcctrl0_reg address : 0x11 description : dcdc high/low power mode control register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch1_ en ch2_ en ch3_ en ch4_ en ch5_ en ch6_ en ldo_ en reserved reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r bits name description 7 ch1_ en 0 : disable 1 : enable (after each uvlo rising, the value is set to 1) 6 ch2_ en 0 : disable 1 : enable (after each uvlo rising, the value is set to 1) 5 ch3_ en 0 : disable 1 : enable (after each uvlo rising, the value is set to 1) 4 ch4_ en 0 : disable 1 : enable (after each uvlo rising, the value is set to 1) 3 ch5_ en 0 : disable 1 : enable (after each uvlo rising, the value is set to 1) 2 ch6_ en 0 : disable 1 : enable (after each uvlo rising, the value is set to 1) 1 ldo_ en 0 : disable 1 : enable (after each uvlo rising, the value is set to 1) 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 29 table 17 . sleep_reg address : 0x12 description : sleep mode control register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch1_ alive ch 2 _ alive ch 3 _ alive ch 4 _ alive ch 5 _ alive ch 6 _ alive ldo _ alive sleep reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bits name description 7 ch1_ alive 0 : when sleep bit = 1 , ch1 turn off 1 : when sleep bit = 1, ch1 alive and enter low power mode 6 ch 2 _ alive 0 : when sleep bit = 1 , ch2 turn off 1 : when sleep bit = 1, ch2 alive and enter low power mode 5 ch 3 _ alive 0 : when sleep bit = 1 , ch3 turn off 1 : when sleep bit = 1, ch3 alive and enter low power mode 4 ch 4 _ alive 0 : when sleep bit = 1 , ch4 turn off 1 : when sleep bit = 1, ch4 alive and enter low power mode 3 ch 5 _ alive 0 : when sleep bit = 1 , ch5 turn off 1 : when sleep bit = 1, ch5 alive and enter low power mode 2 ch 6 _ alive 0 : when sleep bit = 1 , ch6 turn off 1 : when sleep bit = 1, ch6 alive and enter low power mode 1 ldo_ alive 0 : when sleep bit = 1 , ldo turn off 1 : when sleep bit = 1, ldo alive and enter low power mode 0 sleep 0 : e xit sleep mode 1 : enter sleep mode
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 30 table 18 . dcdcctrl1_reg address : 0x13 description : dcdc pskip/pwm mode control register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch1_ pwm ch2_ pwm ch3_ pwm ch4_ pwm ch5_ pwm ch6_ pwm reserved reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r r bits name description 7 ch1_pwm ch1_pwm[7] = 0 : pskip mode. ch1_pwm[7] = 1 : forced pwm mode 6 ch2_ pwm ch2_pwm[6] = 0 : pskip mode. ch2_pwm[6] = 1 : forced pwm mode 5 ch3_ pwm ch3_pwm[5] = 0 : pskip mode. ch3_pwm[5] = 1 : forced pwm mode 4 ch4_ pwm ch4_pwm[4] = 0 : pskip mode. ch4_pwm[4] = 1 : forced pwm mode 3 ch5_ pwm ch5_pwm[3] = 0 : pskip mode. ch5_pwm[3] = 1 : forced pwm mode 2 ch6_ pwm ch6_pwm[2] = 0 : pskip mode. ch6_pwm[2] = 1 : forced pwm mode 1 : 0 reserved reserved bit table 19 . discharge_reg address : 0x14 description : discharge enable register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch1_dis ch2_dis ch3_dis ch4_dis ch5_dis ch6_dis ldo_dis reserved reset value 1 1 1 1 1 1 1 0 read/write r/w r/w r/w r/w r/w r/w r/w r bits name description 7 ch1_dis ch1_dis[7] = 0 : discharge path disable ch1_dis[7] = 1 : discharge path enable 6 ch2_dis ch2_dis[6] = 0 : discharge path disable ch2_dis[6] = 1 : discharge path enable 5 ch3_dis ch3_dis[5] = 0 : discharge path disable ch3_dis[5] = 1 : discharge path enable 4 ch4_dis ch4_dis[4] = 0 : discharge path disable ch4_dis[4] = 1 : discharge path enable 3 ch5_dis ch5_dis[3] = 0 : discharge path disable ch5_dis[3] = 1 : discharge path enable 2 ch6_dis ch6_dis[2] = 0 : discharge path disable ch6_dis[2] = 1 : discharge path enable 1 ldo_dis ldo_dis[1] = 0 : discharge path disable ldo_dis[1] = 1 : discharge path enable 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 31 table 20 . por_option_reg address : 0x17 description : por_option select register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name reserved por_option_sel reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r/w r/w bits name description 7 : 2 reserved reserved bit 0 : 1 por_option_ sel supply state por_option_sel[ 1:0 ] = 00, de pended on avdd por rising with delay time por_option_sel[ 1:0 ] = 01, reserved. por_option_sel[ 1:0 ] = 10, por_option = 0 por_option_sel[ 1:0 ] = 11, por_option = 1 table 21 . dcdctrl 2 _reg address : 0x1 8 description : dcdc high/low power mode control register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch1_ lpm ch2_ lpm ch3_ lpm ch4_ lpm ch5_ lpm ch6_ lpm ldo_ lpm reserved reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r bits name description 7 ch1_lpm ch1_lpm[7] = 0 : active high power mode. ch1_lpm[7] = 1 : active low power mode. 6 ch2_lpm ch2_lpm[6] = 0 : active high power mode. ch2_ lpm[6] = 1 : active low power mode. 5 ch3_lpm ch3_lpm[5] = 0 : active high power mode. ch3_lpm[5] = 1 : active low power mode. 4 ch4_lpm ch4_lpm[4] = 0 : active high power mode. ch4_lpm[4] = 1 : active low power mode. 3 ch5_lpm ch5_lpm[3] = 0 : active high power mode. ch5_lpm[3] = 1 : active low power mode. 2 ch6_lpm ch6_lpm[2] = 0 : active high power mode. ch6_lpm[2] = 1 : active low power mode. 1 ldo_lpm ldo_lpm[1] = 0 : active high power mode. ldo_lpm[1] = 1 : active low power mode. 0 reserved reserved bit
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 32 table 22 . ch 1/ ch 2_wake - up_time address : 0x19 description : . ch 1/ ch 2_wake - up_time bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch1 _wake - up_time ch2 _wake - up_time reset value 0 0 0 0 0 0 0 0 read/write rw rw rw rw rw rw rw rw bits name description 7:4 ch1 _wake - up_time ch1 sleep wake - up sequence disable = 0000 time slot1 = 0001 time slot2 = 0010 time slot3 = 0011 time slot4 = 0100 time slot5 = 0101 time slot6 = 0110 time slot7 = 0111 time slot8 = 1000 time slot9 = 1001 time slot10 = 1010 time slot11 = 1011 time slot12 = 1100 time slot13 = 1101 time slot14 = 1110 time slot15 = 1111 time slot time = 512 ? s 3:0 ch2 _wake - up_time ch2 sleep wake - up sequence disable = 0000 time slot1 = 0001 time slot2 = 0010 time slot3 = 0011 time slot4 = 0100 time slot5 = 0101 time slot6 = 0110 time slot7 = 0111 time slot8 = 1000 time slot9 = 1001 time slot10 = 1010 time slot11 = 1011 time slot12 = 1100 time slot13 = 1101 time slot14 = 1110 time slot15 = 1111 time slot time = 512 ? s
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 33 table 23 . ch3 / ch 4_wake - up_time address : 0x1a description : . ch 3/ ch 4_wake - up_time bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch3 _wake - up_time ch4 _wake - up_time reset value 0 0 0 0 0 0 0 0 read/write rw rw rw rw rw rw rw rw bits name description 7:4 ch3 _wake - up_time ch3 sleep wake - up sequence disable = 0000 time slot1 = 0001 time slot2 = 0010 time slot3 = 0011 time slot4 = 0100 time slot5 = 0101 time slot6 = 0110 time slot7 = 0111 time slot8 = 1000 time slot9 = 1001 time slot10 = 1010 time slot11 = 1011 time slot12 = 1100 time slot13 = 1101 time slot14 = 1110 time slot15 = 1111 time slot time = 512 ? 3:0 ch4 _wake - up_time ch4 sleep wake - up sequence disable = 0000 time slot1 = 0001 time slot2 = 0010 time slot3 = 0011 time slot4 = 0100 time slot5 = 0101 time slot6 = 0110 time slot7 = 0111 time slot8 = 1000 time slot9 = 1001 time slot10 = 1010 time slot11 = 1011 time slot12 = 1100 time slot13 = 1101 time slot14 = 1110 time slot15 = 1111 time slot time = 512 ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 34 table 24 . ch 5/ ch 6_wake - up_time address : 0x1b description : . ch 5/ ch 6_wake - up_time bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ch5 _wake - up_time ch6 _wake - up_time reset value 0 0 0 0 0 0 0 0 read/write rw rw rw rw rw rw rw rw bits name description 7:4 ch5 _wake - up_time ch5 sleep wake - up sequence disable = 0000 time slot1 = 0001 time slot2 = 0010 time slot3 = 0011 time slot4 = 0100 time slot5 = 0101 time slot6 = 0110 time slot7 = 0111 time slot8 = 1000 time slot9 = 1001 time slot10 = 1010 time slot11 = 1011 time slot12 = 1100 time slot13 = 1101 time slot14 = 1110 time slot15 = 1111 time slot time = 512 ? 3:0 ch6 _wake - up_time ch6 sleep wake - up sequence disable = 0000 time slot1 = 0001 time slot2 = 0010 time slot3 = 0011 time slot4 = 0100 time slot5 = 0101 time slot6 = 0110 time slot7 = 0111 time slot8 = 1000 time slot9 = 1001 time slot10 = 1010 time slot11 = 1011 time slot12 = 1100 time slot13 = 1101 time slot14 = 1110 time slot15 = 1111 time slot time = 512 ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 35 table 25 . ldo wake - up_time address : 0x1 c description : ldo_wake - up_time bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name ldo_wake - up_time reserved reset value 0 0 0 0 0 0 0 0 read/write rw rw rw rw r r r r bits name description 7:4 ldo_wake - up_time ldo sleep wake - up sequence disable = 0000 time slot1 = 0001 time slot2 = 0010 time slot3 = 0011 time slot4 = 0100 time slot5 = 0101 time slot6 = 0110 time slot7 = 0111 time slot8 = 1000 time slot9 = 1001 time slot10 = 1010 time slot11 = 1011 time slot12 = 1100 time slot13 = 1101 time slot14 = 1110 time slot15 = 1111 time slot time = 512 ? 3:0 reserved reserved bits table 26 . product_id_reg address : 0x20 description : product id number register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name product_id reset value 0x01 read/write r r r r r r r r bits name description 7 : 0 product_id return the product id number : 0x01
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 36 table 27 . manufacturer_id_reg address : 0x21 description : manufacturer id number register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name manufacturer_id reset value 0x01 read/write r r r r r r r r bits name description 7 : 0 manufacturer_id return the manufacturer id number : 0x01 table 28 . revision_number_reg address : 0x22 description : revision number register. bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name revision_number reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r bits name description 7 : 0 revision_number return the revision number : 0x00
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 37 typical operating characteristics ch1 efficiency vs. output current 80 82 84 86 88 90 92 94 96 98 100 0.5 1 1.5 2 2.5 3 3.5 4 output current (a) efficiency (%) v out = 2.5v v in = 3.3v v in = 5v ch2 efficiency vs. outputcurrent 70 75 80 85 90 95 100 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v out = 1.35v v in = 3.3v v in = 5v ch3 efficiency vs. output current 80 82 84 86 88 90 92 94 96 98 100 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v out = 1.8v v in = 3.3v v in = 5v ch4 efficiency vs. load current 70 75 80 85 90 95 100 0.5 0.75 1 1.25 1.5 1.75 2 load current (a) efficiency (%) v out = 1v v in = 3.3v v in = 5v ch5 efficiency vs. output current 70 75 80 85 90 95 100 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v out = 1v v in = 3.3v v in = 5v ch6 efficiency vs. output current 70 75 80 85 90 95 100 0.5 1 1.5 2 2.5 3 3.5 output current (a) efficiency (%) v out = 1v v in = 3.3v v in = 5v
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 38 ch1 output voltage vs. output current 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 0 0.5 1 1.5 2 2.5 3 3.5 4 output current (a) output voltage (v) v out = 2.5v v in = 3.3v v in = 5v ch2 output voltage vs. output current 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 0 0.2 0.4 0.6 0.8 1 output current (a) output voltage (v) v out = 1.35v v in = 3.3v v in = 5v ch3 output voltage vs. output current 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 0 0.2 0.4 0.6 0.8 1 output current (a) output voltage (v) v out = 1.8v v in = 3.3v v in = 5v ch4 output voltage vs. output current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 output current (a) output voltage (v) v out = 1v v in = 3.3v v in = 5v ch5 output voltage vs. output current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0 0.2 0.4 0.6 0.8 1 output current (a) output voltage (v) v out = 1v v in = 3.3v v in = 5v ch6 output voltage vs. output current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0 0.5 1 1.5 2 2.5 3 3.5 4 output current (a) output voltage (v) v out = 1v v in = 3.3v v in = 5v
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 39 ch1 output voltage vs. input voltage 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 2.5v i out = 1a i out = 2a i out = 4a ch2 output voltage vs. input voltage 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 1.35v i out = 0.5a i out = 1a ch3 output voltage vs. input voltage 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 1.8v i out = 0.5a i out = 1a ch4 output voltage vs. input voltage 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 1v i out = 2a i out = 1a ch5 output voltage vs. input voltage 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 1v i out = 0.5a i out = 1a i out = 0.25a ch6 output voltage vs. input voltage 0.990 0.993 0.995 0.998 1.000 1.003 1.005 1.008 1.010 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 1v i out = 2a i out = 1a
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 40 v in = 3.3v , v out = 2.5v , i out = 2a to 4 a v out (50mv/ div ) i out (1a/ div ) time (100 ? s/ div ) ch1 load transient response v out (10mv/ div ) i out (500ma/ div ) time (200 ? s/ div ) ch2 load transient response v in = 3.3v , v out = 1.35v , i out = 0.5a to 1 a v out ( 20mv/ div ) i out (500ma/ div ) time (2 00 ? s / div ) ch3 load transient response v in = 3.3v , v out = 1.8v , i out = 0.5a to 1 a v in = 3.3v , v out = 1v , i out = 1 a to 2a v out ( 20mv/ div ) i out ( 1 a/ div ) time (200 ? s/ div ) ch4 load transient response v in = 3.3v , v out = 1 v , i out = 0.5a to 1a v out ( 20mv/ div ) i out (500ma/ div ) time ( 200 ? s / div ) ch5 load transient response v in = 3.3v , v out = 1 v , i out = 1.5a to 3.5a v out ( 20mv/ div ) i out ( 2 a/ div ) time (400 ? s/ div ) ch6 load transient response
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 41 ch1 output voltage vs. temperature 2.48 2.49 2.50 2.51 2.52 2.53 2.54 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v out = 2.5v, i out = 0a v in = 3.3v v in = 3v ch2 output voltage vs. temperature 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v out = 1.35v, i out = 0a v in = 3.3v v in = 2.9v ch3 output voltage vs. temperature 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v out = 1.8v, i out = 0a v in = 3.3v v in = 2.9v ch4 output voltage vs. temperature 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v out = 1v, i out = 0a v in = 3.3v v in = 2.9v ch5 output voltage vs. temperature 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v out = 1v, i out = 0a v in = 3.3v v in = 2.9v ch6 output voltage vs. temperature 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v out = 1v, i out = 0a v in = 3.3v v in = 2.9v
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 42 application information the RT5045A provides six synchronous b uck regulators and one ldo to satisfy the entire power system of ssd. this device can communicate with processors through i 2 c interface for programming the voltage, monitoring the status, or in/out the power saving mode. table 29 lists the power rails provided by the RT5045A. table 29 . detail of power rails resource name type voltage range current rating ch1 buck converter 2.3 v C 3.0v, 25mv step 4 000 ma ch2 buck converter 0.9 v C 1.6v, 25mv step 1000 ma ch3 buck converter 1.5v C 2.1v, 25mv step 1000 ma ch4 buck converter 0.7 v C 1.3v, 25mv step 2000 ma ch5 buck converter 0. 7 v C 1.3v, 25mv step 1000 ma ch6 buck converter 0.7 v C 1.3v, 25mv step 3500m a ldo ldo 2.3v C 3.0v, 25mv step 1.656v - 2.16v,18mv step 200 ma buck converter the RT5045A incorporates six high - efficiency synchronous switching b uck converters that deliver various voltages. ch1 features peak current mode architecture of b uck converter. for preventing the unstable when duty > 50% traditionally, it adds external ramp and compensation to reduce duty cycle perturbation and stabilize t he current loop. ch1 can operate up to 100% duty to let the lowest input voltage still maintain the regulator work. and the output voltage will be the lowest input voltage decreases dropout voltage on the resistance of current path. unlike ch1, the control scheme of other buck converters are constant - on - time current mode for low output voltage, quick transient response. every switching regulator is specially designed for very low quiescent (<20 ? a), high - efficiency operation throughout the load range. with high switching frequency (1m to 3mhz), the external lc filter can be small and keep s very low output voltage ripple. additional features include soft - start, discharged, input uvlo protection, under - voltage protection, over voltage protection, over current protection and over thermal protection. please note that the ic will latched when one power rail occurs under voltage protection. the other protections just make the rail output voltage drop and recovery when the faults disabled. with i 2 c interface, every b uck converter can program output voltage, adjust vid slew rate, change the pwm frequency, and control the on/off state. even pwm can switch to forced pwm mode, pskip mode or lpm mode (quiescent < 10 ? a). please see the back register tables for detail contr ol. inductor selection for given input voltage (v in ), output voltage (v out ), and operation frequency (f sw ), the inductor value (l) determines the inductor ripple current ( ? i l ) as shown in equation below : having a lower ripple current reduces not only the esr losses in the output capacitors, but also the output voltage ripple. a reasonable starting point for selecting the ripple current is ? i l = 0.3i max to 0.4i max . the largest ripple current occurs at the highest vin. to guara ntee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : ? ? out in out l sw in v v v i f l v ?? ?? ??
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 43 t he current rating of the inductor must be large enough and will not saturate at the peak inductor current (i peak ) : c in and c sys s election the input capacitance of every rail, c in , needs to filter the trapezoidal current at the source of the high - side mosfet. to prevent large ripple voltage, a low esr input capacitor for the maximum current should be used. the relation between c in ripple voltage and current ripple is shown as the figure 1. figure 1. relationship of c in voltage ripple and current ripple the c in voltage ripple can use below equations to determine when f sw works at ccm mode. where d = v out / v in . if use mlcc as the input current, the esr is almost equal to zero. and the minimum input capacitance requirement could be estimate as below : next, it needs to consider the input bulk capacitance, c sys , to ensure a stable input voltage during large load transient. the input host supply can not typically provide the enough input current for the converter to respond to a fast transient current. the input bulk capacitor will provide the energy necessary to source current until the host supply fill the demand, as shown as figure 2. figure 2. charge required from input bulk capacitor during transient . ? ? ? ? ? ? out out in max sw l in max v v v l= f i v ?? ? ? ? ? ? l peak out max i ii 2 ? ?? c i n r i p p l e v o l t a g e c i n r i p p l e c u r r e n t v = d i o u t e s r v p p d i o u t - ( 1 - d ) i o u t t o n t o f f d = 0 . 5 d v = d i o u t d t / c i n ? ? ? ? cin_pp out max in sw 1d v d i esr+ cf ?? ? ? ? ? ?? ?? ? ?? ? ? ? ? ? ? ? ? in min out max sw cin_pp max d 1 d ci vf ?? ?? ? i n p u t s u p p l y c u r r e n t c h a r g e r e q u i r e d f r o m b u l k c a p a c i t o r t o t a l i n p u t r e s p o n d e d t r a n s i e n t r e q u i r e d i i n t r t r i t
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 44 figure 3 shows the diagram of every power rail of RT5045A sharing a single bank of bulk input capacitors. it can calculate the input required transient current using following equation : where ? i intr is the total input transient current required. ? i out is the maximum output transient current. is the efficiency of the b uck at i out(max) . figure 3. the location of b ulk input capacitance diagram when ? i intr is confirmed, the input bulk capacitance, c sys , can be decided with following estimating equation: w here ? v inpp(max) is the maximum ac voltage allowable. l in is the input series filter inductance, if not used, put a reasonable v alue 50nh due to pcb layout. c out selection the output capacitor and the inductor form a low pass filter in the buck topology. in steady state condition, the ripple current flowing into/out of the capacitor results in ripple voltage. the output voltage ripple ( ? v outpp ) can be calculated by the following equation: when load transient occurs, the output capacitor supplies the load current before the controller can respond. therefore, the esr will dominate the output voltage sag d uring load transient. the output voltage under - shoot (v sag ) can be calculated by the following equation : for a given output voltage sag specification, the esr value can be determined. another parameter that has influence on the output voltage sag is the equivalent series inductance (esl). the rapid change in load current results in di/dt during transient. therefore, the esl contributes to part of the voltage sag. using a capacitor with low esl can obtain better transient performa nce. generally, using several capacitors connected in parallel can have better transient performance than using a single capacitor for the same total esr. unlike the electrolytic capacitor, the ceramic capacitor has relatively low esr and can reduce the vo ltage deviation during load transient. however, the ceramic capacitor can only provide low capacitance value. therefore, use a mixed combination of electrolytic capacitor and ceramic capacitor to obtain better transient performance. vsel0, vsel1 the rt5045 a appl ies four set default output voltages for all power rails when the device starts a power up sequence. the detail of the initial output voltages shows in table 30 lists the power rails provide by the RT5045A. table 30 vsel0 0 0 1 1 vsel1 0 1 0 1 ch1 2.5v 2.5v 2.5v 2.5v ch2 1.35v 1.35v 1.35v 1.2v ch3 1.8v 1.8v 1.8v 1.8v ch4 1.0v 1.0v 1.2v 1.2v ch5 1.0v 1.0v 0.9v 0.9v ch6 1.0v 1.0v 0.9v 0.9v ldo 2.5v 2.5v 1.8v 1.8v por delay time 10ms 10ms 6ms 6ms porsel porsel is a logic pin to select the threshold voltage of avdd to raise por signal. if avdd voltage is over the threshold voltage, the device start s a por rising function. when set porsel = 1, the threshold voltage of avdd is 3.8v, else the threshold voltage is 2.8v. por_option please refer to the following table to realize the por_option setting. ? ? 6 outn outn max intr in n n=1 vi i v ?? ?? ? ? c s y s c h 1 c i n 1 c h 2 . . . c h 6 c i n 2 c i n 6 . . . l i n v i n ? ? ? ? 2 intr in sys min 2 inpp max 1.21 i l c v ? ? ? ? ? outpp l out sw 1 v i esr 8 c f ?? ? ? ? ? ?? ?? ?? sag load v i esr ? ? ?
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 45 table 31 . por_option value setting condition por_option_reg por_option_sel [0:1] description 0x00 por_option = 0 0x01 reversed. 0x02 por_option = 0 0x03 por_option = 1 por por pin is a signal to inform the system that the power up sequence of the RT5045A is completed. at por_option = 0 situation . if avdd voltage is less than 100mv than vporth, the por falls right away. when the device gets por_option = 1, por will fall after sleep[0] = 0 turns to sleep[0] = 1, and por comes after sleep [0] = 1 turn to sleep[0] = 0 with a 8ms delay. i 2 c interface the rt50 45 a i 2 c slave address = 0x1b (hex). i 2 c interface su pports standard slave mode (100 k bps), and fast mode (400 k bps). the write or read bit stream (n ? 1) is shown below : figure 4. i 2 c read and write stream and timing diagram s 0 1 a p l s b m s b a a s s u m e a d d r e s s = m d a t a f o r a d d r e s s = m d a t a f o r a d d r e s s = m + n - 1 a d a t a f o r a d d r e s s = m + 1 s 0 p a s s u m e a d d r e s s = m d a t a f o r a d d r e s s = m d a t a f o r a d d r e s s = m + n - 1 d a t a f o r a d d r e s s = m + 1 s r s l a v e a d d r e s s r e g i s t e r a d d r e s s s l a v e a d d r e s s d a t a 1 r / w r / w d a t a n l s b m s b a a a a a a a a r e a d n b y t e s f r o m r t 5 0 4 5 a l s b m s b d a t a 2 d a t a n l s b m s b l s b s l a v e a d d r e s s r e g i s t e r a d d r e s s d a t a 1 d a t a 2 m s b m s b l s b w r i t e n b y t e s t o r t 5 0 4 5 a d r i v e n b y m a s t e r , d r i v e n b y s l a v e ( r t 5 0 4 5 a ) , s t a r t , r e p e a t s t a r t s t o p , s s r p s d a s c l t f t l o w t h d , s t a t h d , d a t t h i g h t s u , d a t t s u , s t a t h d , s t a t s p t b u f t s u , s t o p s t r s r s t f t r
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 46 serial data transfer format in hs - mode serial data transfer format in hs - mode meets the standard - mode i 2 c - bus specification. hs - mode can only commence after the following conditions (all of which are in f/s - mode) : ? start condition (s) ? 8 - bit master code (00001 xxx ) ? not - acknowledge bit ( ) figures 5 and figure 6 show this in more detail. this master code has two main functions: ? ? it allows arbitration and synchronization between competing masters at f/s - mode speeds, resulting in one winning master. ? ? it indicates the beginning of an hs - mode transfer. hs - mode mast er codes are reserved 8 - bit codes, which are not used for slave addressing or other purposes. furthermore, as each master has its own unique master code, up to eight hs - mode masters can be present on the one i 2 c - bus system (although master code 0000 1000 s hould be reserved for test and diagnostic purposes). the master code for an hs - mode master device is software programmable and is chosen by the system designer. arbitration and clock synchronization only take place during the transmission of the master cod e and not - acknowledge bit ( ), after which one winning master remains active. the master code indicates to other devices that an hs - mode transfer is to begin and the connected devices must meet the hs - mode specification. as no device is allowed to acknowledge the master code, the master code is followed by a not - acknowledge ( ). after the not - acknowledge bit ( ), and the sclh line has been pulled - up to a high level, the active ma ster switches to hs - mode and enables (at time t h , see fig ure 6 ) the current - source pull - up circuit for the sclh signal. as other devices can delay the serial transfer before t h by stretching the low period of the sclh signal, the active master will enable its current - source pull - up circuit when all devices have released the sclh line and the sclh signal has reached a high level, thus speeding up the last part of the rise time of the sclh signal. the active master then sends a repeated start condition (sr) f ollowed by a 7 - bit slave address (or 10 - bit slave address, see section 14) with a r/w bit address, and receives an acknowledge bit ( ) from the selected slave. after a repeated start condition and after each acknowledge bit ( ) or not - acknowledge bit ( ), the active master disables its current - source pull - up circuit. this enables other devices to delay the serial transfer by stretching the low period of the sclh signal. the active ma ster re - enables its current - source pull - up circuit again . w hen all devices have released and the sclh signal reaches a high level, and so speeds up the last part of the sclh signals rise time. data transfer continues in hs - mode after the next repeated start (sr), and only switches back to f/s - mode after a stop condition (p). to reduce the overhead of the master code, its possible that a master links a number of hs - mode transfers, separated by repeated start conditions (sr). figure 5 . data transfer format in hs - mode a s m a s t e r c o d e a s r r / w a d a t a a / a h s - m o d e c o n t i n u e s f / s - m o d e h s - m o d e ( c u r r e n t - s o u r c e f o r s c l h e n a b l e d f / s - m o d e p n b y t e s + a c k . s l a v e a d d . s r s l a v e a d d .
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 47 figure 6 . a complete hs - mode transfer power on / off s equence the RT5045A start s a power up sequence when avdd > uvlo rising threshold voltage , a nd the device shuts down with avdd < uvlo falling threshold voltage. the RT5045A applies sleep mode of pmic to save power consumption with setting the sleep bit of sleep_reg to 1. if the device goes to sleep mode, power rails are se t to lpm and the alive rails depend on sleep mode control register setting. the power rails will exit from lpm to normal mode and wake up with a sequence as the same as the power - up - sequence when sleep bit = 0. the relations of all power rails of RT5045A and sleep off / wake up sequence with different por_option on v in = 3.3v are shown as following figure 7 . the relations of all power rails of RT5045A and sleep off / wake up sequence with different por_option on v in = 5v are shown as following figure 8 . figure 7 . for example : power on/off sequence and sleep off / wake up sequence with different por_option on v in = 5 v s s d a h s c l h 8 - b i t m a s t e r c o d e 0 0 0 0 1 x x x a t 1 t h 1 2 t o 5 6 7 8 9 f / s - m o d e s d a h s c l h s r 7 - b i t s l a r / w a n x ( 8 - b i t d a t a + a / a s r p 1 2 t o 5 6 7 8 9 1 2 t o 5 6 7 8 9 h s - m o d e i f p t h e n f / s m o d e i f s r ( d o t t e d l i n e s ) t h e n h s - m o d e t f s t h = m c s c u r r e n t s o u r c e p u l l - u p = r p r e s i s t o r p u l l - u p a v d d c h 5 c h 4 c h 6 c h 2 c h 3 l d o c h 1 3 . 8 v 5 v p o r ( p o r _ o p t i o n = 0 ) t i m e s l o t 1 t i m e s l o t 2 t i m e s l o t 3 t i m e s l o t 4 t i m e s l o t 5 t i m e s l o t 6 t i m e s l o t 7 1 5 0 u s t i m e s l o t 8 t i m e s l o t 1 5 3 . 7 v p o r ( p o r _ o p t i o n = 1 ) 5 v t i m e s l o t 1 t i m e s l o t 2 t i m e s l o t 3 t i m e s l o t 4 t i m e s l o t 5 t i m e s l o t 6 t i m e s l o t 7 t i m e s l o t 8 t i m e s l o t 1 5 t d e l a y t d e l a y e n t e r s l e e p e x i t s l e e p v s e l 0 = 0 , t d e l a y = 1 0 m s v s e l 0 = 1 , t d e l a y = 6 m s
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 48 figure 8 . for example : power on/off sequence and sleep off / wake up sequence with different por_option on v in = 3.3 v the relations quiescent current and lpm current of each channel table are shown as below . rt5045 pmode1 pmode2 pmode3 pmode4 pmode5 pmode6 pmode7 pmode8 buck1 2. 5 v on off off off off off off off buck2 1.35v on on off off off off off off buck3 1.8v on on on off off off off off buck4 1.0v on on on on off off off off buck5 1.0v on on on on on on on on buck6 1.0v on on on on on on off off ldo 2.5v on on on on on off off off lpm off off off off off off off on lpm all off total ( ? a v d d c h 5 c h 4 c h 6 c h 2 c h 3 l d o c h 1 2 . 8 v 3 . 3 v p o r ( p o r _ o p t i o n = 0 ) t i m e s l o t 1 t i m e s l o t 2 t i m e s l o t 3 t i m e s l o t 4 t i m e s l o t 5 t i m e s l o t 6 t i m e s l o t 7 1 5 0 u s t i m e s l o t 8 t i m e s l o t 1 5 2 7 v p o r ( p o r _ o p t i o n = 1 ) 3 . 3 v t i m e s l o t 1 t i m e s l o t 2 t i m e s l o t 3 t i m e s l o t 4 t i m e s l o t 5 t i m e s l o t 6 t i m e s l o t 7 t i m e s l o t 8 t i m e s l o t 1 5 t d e l a y t d e l a y e n t e r s l e e p e x i t s l e e p v s e l 0 = 0 , t d e l a y = 1 0 m s v s e l 0 = 1 , t d e l a y = 6 m s
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 49 thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperatu re. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ? ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ? ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 ? c. the junction to ambient thermal resistance, ? ja , is layout dependent. for wl - csp - 52b 3.19x3.59 (bsc ) package, the thermal resistance, ? ja , is 26 ? c/w on a standard je dec 51 - 7 four - layer thermal test board. the maximum power dissipation at t a = 25 ? c can be calculated by the following formula : p d(max) = (125 ? c ? 25 ? c) / ( 26 ? c/w) = 3.84 w for wl - csp - 52b 3.19x3.59 (bsc ) the maximum power dissipation depends on the op erating ambient temperature for fixed t j(max) and thermal resistance, ? ja . the derating curve in figure 9 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 9 . derating curve of maximum power dissipation layout considerations layout is very important in high frequency switching converter design. the pcb can radiate excessive noise and contribute to converter instability with improper layout. power components should be p laced on the same side of board, with power traces routed on the same layer. if it is necessary to route a power trace to another layer, choose a trace in low di/dt paths and use multiple vias for interconnection. when vias are used to connect pcb layers i n the high current loop, multiple vias should be used to minimize via impedance. certain points must be considered before starting a layout using the rt50 45 a. ? make the traces of the main current paths as short and wide as possible. ? place input decoupling c apacitors as close as ossible as to pvin1 pvin2 pvin3 pvin4 pvin5 pvin6 . this cap provide the instant current into this pin when the internal mosfet switching. it is preferable to connect the decoupling capacitors directly to the pins without using vias . ? place the inductors close lx1 lx2 lx3 lx4 lx5 lx6 . to minimize the radiation noise, and the copper area should be minimized. however, the copper area is provided a heat sink to the internal mosfet. dont make the area of the node small by using narrow tra ces, using wide and short traces instead. ? for feedback signals fb1 fb2 fb3 fb4 fb5 fb6 , the sensing point which detects the output voltage must be connected after output capacitor and keep the trace far away from the switching node or inductor. place the f eedback network as close to the chip as possible. ? place the bypass capacitor close to avdd . ? place the filter capacitor close to ldo lx1 lx2 lx3 lx4 lx5 lx6 to minimize trace inductance. ? the gnd pin and exposed pad should be connected to a strong ground pla ne for heat sinking and noise protection. 0.0 1.0 2.0 3.0 4.0 5.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5045a - 00 march 2015 50 ? an example of pcb layout guide is shown in figure 7.for reference. figure 10 . pcb layout guide a 1 a 2 s c l a 3 a 4 a 5 a 6 a 7 a 8 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 c 1 c 2 c 7 c 8 d 8 d 7 d 2 d 1 e 1 e 2 e 7 e 8 f 8 f 7 f 2 f 1 g 1 g 2 g 7 g 8 h 8 h 7 h 6 h 5 h 4 h 3 h 2 h 1 j 8 j 7 j 6 j 5 j 4 j 3 j 2 j 1 s d a l d o a v d d a g n d a g n d p o r f b 6 p g n d p g n d f b 1 v s e l 0 v s e l 1 p o r s e l p g n d 6 p g n d 6 p g n d p v i n 3 l x 2 p g n d 3 / 4 l x 4 l x 3 p v i n 4 p v i n 5 f b 3 p v i n 3 p v i n 2 p g n d 3 / 4 l x 4 l x 3 p v i n 4 f b 4 p g n d 1 p g n d 1 l x 6 l x 6 l x 1 l x 1 p v i n 6 p v i n 6 p v i n 1 p v i n 1 p g n d f b 5 p g n d f b 2 p g n d p g n d 5 p g n d p g n d 2 p g n d l x 5 v o u t c h 6 p v i n v o u t c h 5 g n d g n d p v i n v o u t c h 4 v o u t c h 3 g n d p v i n g n d v o u t c h 2 p v i n g n d v o u t c h 1 p v i n g n d g n d g n d g n d i n p u t c a p a c i t o r m u s t b e p l a c e d a s c l o s e t o t h e i c a s p o s s i b l e i n p u t c a p a c i t o r m u s t b e p l a c e d a s c l o s e t o t h e i c a s p o s s i b l e l x s h o u l d b e c o n n e c t e d t o i n d u c t o r b y w i d e a n d s h o r t t r a c e . k e e p s e n s i t i v e c o m p o n e n t s a w a y f r o m t h i s t r a c e . l x s h o u l d b e c o n n e c t e d t o i n d u c t o r b y w i d e a n d s h o r t t r a c e . k e e p s e n s i t i v e c o m p o n e n t s a w a y f r o m t h i s t r a c e . t h e o u t p u t c a p a c i t o r m u s t b e p l a c e d n e a r t h e i c i n p u t c a p a c i t o r m u s t b e p l a c e d a s c l o s e t o t h e i c a s p o s s i b l e i n p u t c a p a c i t o r m u s t b e p l a c e d a s c l o s e t o t h e i c a s p o s s i b l e p v i n t h e o u t p u t c a p a c i t o r m u s t b e p l a c e d n e a r t h e i c t h e o u t p u t c a p a c i t o r m u s t b e p l a c e d n e a r t h e i c t h e o u t p u t c a p a c i t o r m u s t b e p l a c e d n e a r t h e i c
RT5045A copyright ? 2015 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5045a - 00 march 2015 www.richtek.com 51 outline dimension symbol dimensions in millimeters dimensions in inches min. max. min. max. a 0.500 0.600 0.020 0.024 a1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 d 3.540 3.640 0.139 0.143 d1 3.200 0.126 e 3.140 3.240 0.124 0.128 e1 2.800 0.110 e 0.400 0.016 5 2b wl - csp 3.19 x 3.59 package (bsc) richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications witho ut notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should ver ify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnished by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent righ ts of richtek or its subsidiaries.

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